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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Features General Description
* Operation Voltage 2.5V~6.0V The AT1367A/B/C/D provides complete * Oscillation frequency 1MHz control for a DC/DC converter optimized for * Output Current Maximum 800mADC-DC hight-performance microprocessor applications. It Converter consists of a synchronous step-down DC/DC * Built-In 400mA/LDO converter and a high-speed LDO regulator * Power Good Indicator with Time Delay connected in series with the DC/DC converter Adjustable output. A power good detector and LDO ON/OFF * Built-In Current Limit control is also built-in(metal option). DC/DC * Built-In UVLO converter is operated on current mode architecture * Built-In Thermal ShutDown for excellent line and load transient response. * Built-In LDO ON/OFF ControlMetal Option 1MHz operation frequency is allowing the use of small surface mount inductor and capacitor. The internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. The AT1367A/B/C/D is a family of Applications low-noise synchronous step-down DC/DC * Power Supply for Slim Type devices converters that is ideally suited for systems powered form a 1-cell Li-ion battery or from a 3-cell to 4-cell NiCd, NiMH, or alkaline battery. It can also be used to USB-based power system.
Block Diagram
VBG VBG Vref VREG UVLO VCC
Current Sense
5
AGND
+
SLOPE
+ R S SW Q
OSC CTL Control LDO R5 DELAY Auto Discharge *CTL and /PG Metal Option PG UVLO /PG CTL Vref + VCC 0.9 x Vref 0.35uA -
Shoot Throught
PGND R2 R1 OUT1 Current Limit R3 + CTL + Vref *OUT2=2.5V/1.8V Metal Option Vref R4 OUT2
Aimtron reserves the right without notice to change this circuitry and specifications.
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 3/2/2006 REV:1.2 Email: service@aimtron.com.tw 1
AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Pin Assignment
1 2 3 4 5
DFN10 (TOP VIEW)
10 9
AT1367A /PG LDO 2.5V AT1367B /PG LDO 1.8V AT1367C CTL LDO 2.5V AT1367D CTL LDO 1.8V
AT1367
8 7 6
Ordering Information
Part Number 1367 N A:1367AN Date Code *For more marking information, contact our sales representative directly. Package DFN10,Green B:1367BN C:1367CN D:1367DN Marking
Pin Description Symbol
PG /PG or CTL VCC SW PGND VBG AGND DELAY OUT1 OUT2
Pin No.
1 2 3 4 5 6 7 8 9 10
Descript
Power Good Indicator Output(Ative Hi) /Power Good Output (Ative Lo) or LDO ON/OFF Control ( Metal Option ) Power Supply OUT1 Inductor Node Power Ground Reference Output Voltage Analog Ground The capacitor connection terminal for a reset delay time setup LDO Intput and DC/DC Output LDO Output
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Absolute Maximum Ratings*1 Parameter
Power Supply Voltage Input Pin Voltage P-Channel Switch Source Current (DC) N-Channel Switch Sink Current (DC) Peak SW Sink and Source Current Thermal Resistance from Junction to Ambient JA Thermal Resistance from Junction to Case JC Operating temperature TA Storage temperature ESD Susceptibility*2
Symbol
VCC CTL, OUT1, OUT2 SW, PG, /PG -- -- -- DFN10 DFN10 -- -- HBM MM
Rated Value Min. Max.
-0.3 -0.3 -0.3 -35 -55 +6.5 VCC VCC+0.3 1 1 1.5 35.25 3 +85 +150 2 200
Unit
V V V A A A
0
C/W C/W
0 0
0
C C
KV V
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Device are ESD sensitive. Handling precaution recommended. The Human Body model is a 100pF capacitor discharged through a 1.5K resistor into each pin.
Recommended Operating Conditions
(Ta=+250C)
Parameter
Power supply voltage Operating temperature* Operating junction temperature *Using X5R or X7R input capacitors.
Symbol
VIN TOP TJ
Min.
2.5 -20 -
Values Typ. Max.
-+25 6.0 +85 +150
Unit
C C
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 3/2/2006 REV:1.2 Email: service@aimtron.com.tw 3
AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Electrical Characteristics
(VCC = 3.6V,Ta =+25 , unless otherwise noted. )
Parameter
DC/DC CONVERTER
VCC UVLO UVLO Hysteresis width Input Supply Range Quiescent Current Output1 Voltage Accuracy Output1 Voltage line-regulation Output1 Variation with Temperature Feedback current Current Limit Maximum Output Current Oscillator Frequency RDS(ON) of P-Channel MOSFET RDS(ON) of N-Channel MOSFET SW Leakage Current
Symbol
Condition
Values Unit Min. Typ. Max.
2.5 2.4 100 500 0.1 0.5 6 1.25 1.0 200 0.3 0.25 0.1 1.0 6 80 80 0.5 400 15 0.05 60 6 6.0 +2 0.5 1.0 1.50 800 1.2 -0.4 0.35 1 1.5 0.4 1 0.4 1 0.8 +2 600 50 0.25 V mV V A % % % uA A mA MHz KHz A V A V mV uA V mV uA uA % mA mV mV % dB uA
VUV VUVHY VCC IS VOUT1
VCC=3V2V Sweep
Active Mode
-2 1.10 0.8 -
VOUT1-Line VCC=3.5V to 6.0V Ta =-20 to +85 IOUT1 ICL1 IO fosc1 fosc2 RPFET RNFET ISWL VOUT1=3.3V VIN=5V, VOUT1=3.3V VIN=5V, VOUT1=3.3V, L=4.7uH Vout1=3.3V Vout1=0V ILX= 600mA ILX= -600mA
CONTROL BLOCK
CTL Threshold VCTL CTL leakage Current ICTL PG on voltage VPGON PG Hysteresis width VPGTHYS PG pin leak current IPGTLK /PG on voltage V/PGON /PG Hysteresis width V/PGTHYS /PG pin leak current I/PGTLK DELAY Pin Charge Current IDELAY Metal Option 0.3 VCTL=0V~2V sweep VCTL=5.0VMetal Option IPG=1mA V/PG=5.0V I/PG=1mAMetal Option Metal Option V/PG=5.0VMetal Option 0.3 -2 450 VOUT1=3.3V IOUT2=400mA IOUT2=1mA 100mA IOUT2=100mA, VOUT1=3.5V6.0V IOUT2=100mA, f=1kHz CTL=0V, VOUT2=2.5V/1.8VMetal Option
LDO
Output2 Voltage Accuracy Current Limit Dropout Voltage Load Regulation Line Regulation Ripple Rejection Rate OUT2 Leakage Current VOUT2 ICL2 VDV VOUT2 LR PSRR IOUT2LK
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 3/2/2006 REV:1.2 Email: service@aimtron.com.tw 4
AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Typical characteristics
Efficiency VS. Output1 Current 100 95 90 85 Efficiency(%)
Efficiency VS. Output1 Current 100 95 90 85 Efficiency(%) 80 75 70 65 60 55 50 VCC=5V VCC=4.2V VCC=3.6V
80 75 70 65 60 55 50 10 100 Output1 Current(mA) 1000 L=2.2uH L=3.3uH L=4.7uH
10
100 Output1 Current(mA)
1000
CH1Vin, CH2Vout1, CH3PG, CH4/PG
CH1Vout1, CH2Vout2, CH3PG, CH4CTL
CH1Vout1, CH2Vout2, CH4Iout1 Iout1=100mA~400mA, Iout2=300mA
CH1Vout1, CH2Vout2, CH4Iout2 Iout1=300mA, Iout2=100mA~300mA
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 3/2/2006 REV:1.2 Email: service@aimtron.com.tw 5
AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Typical Application Circuits
VBG 10nF AGND
VCC 10uF 4.7uH SW
VIN 5.0V
DELAY 10uF 27nF To DSP /PG OUT1 To DSP PG OUT2 100K 100K VOUT2 2.5V/400mA 2.2uF
VOUT1 3.3V/300mA
AT1367A
PGND
Figure 1
VBG 10nF AGND
VCC 10uF 4.7uH SW
VIN 5.0V
DELAY 10uF 27nF
VOUT1 3.3V/300mA
AT1367B
/PG PG
PGND
To DSP To DSP
OUT1 OUT2
VOUT2 1.8V/400mA 2.2uF
100K
100K
Figure 2
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Typical Application Circuits ( Continued )
From DSP CTL VBG 10nF SW DELAY 10uF 27nF AGND OUT1 To DSP PG OUT2 100K VCC 10uF 4.7uH
VIN 5.0V
VOUT1 3.3V/400mA
AT1367C
PGND
VOUT2 2.5V/400mA 2.2uF
Figure 3
From DSP CTL VBG 10nF SW DELAY 10uF 27nF AGND OUT1 To DSP PG OUT2 100K VCC 10uF 4.7uH
VIN 5.0V
VOUT1 3.3V/400mA
AT1367D
PGND
VOUT2 1.8V/400mA 2.2uF
Figure 4
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 3/2/2006 REV:1.2 Email: service@aimtron.com.tw 7
AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Typical Application Circuits ( Continued )
VIN 5.0V 10uF AGND 4.7uH SW DELAY 10uF 27nF To DSP /PG OUT1 To DSP PG OUT2 100K 100K VOUT2 1.8V/400mA 2.2uF From /PG 0.1uF 1M VOUT1 3.3V/300mA
VBG 10nF
VCC
AT1367B
PGND 100K
Figure 5
Application Information Capacitor Selection In continuous mode, the source current of the top MOSFET is square wave of duty cycle. The Primary function of the input capacitor is to provide a low impedance loop for the edges of pulsed current drawn by the AT1367A/B/C/D. A load step at the output can induce ringing at the input VIN. This ringing can couple to the output and be mistaken as loop instability. The oscillation can be improved by add the capacitance of the input capacitor. A typical value is 10F ceramic (X5R or X7R), POSCAP or Aluminum Polymer. These capacitors will provide good high frequency bypassing and their low ESR will reduce resistive losses for higher efficiency. The input capacitor RMS current varies with the input voltage and the output voltage. The equation for the maximum RMS current in the input capacitor is:
VO V (1 - O ) VIN VIN
I RMS = I OMAX
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO The output capacitor depends on the suitable ripple voltage. Low ripple voltage corresponds to lower effective series resistance (ESR). The output ripple voltage is determined by:
VOUT I L ( ESR +
1 ) 8 fC OUT
The output capacitor RMS ripple current is given by:
I RMS = 1 VOUT x (VIN - VOUT ) L x f x VIN 23
VBG Capacitor A VBG pin is provided to decouple the bandgap reference voltage. An external capacitor connected form VBG to GND reduces noise present on the internal reference voltage, which in turn significantly reduces output noise and also improves PSRR. Larger capacitor values may be used to further improve PSRR, but result in a longer time period (slower turn on) to settle output voltage when power is initially applied.
LDO For general purposes, use a 2.2uF capacitor on the LDO output. Larger capacitor values and lower ESR provide better supply noise rejection and transient response. A higher value input capacitor may be necessary if large, fast transients are anticipated . Ceramic capacitors have the lowest ESR, and will offer the best AC performance. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
Inductor Selection The inductor is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple current. Always consider the losses associated with the DCR and its effect on the total converter
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO
efficiency when selecting an inductor. The inductor is selected to limit the ripple current to some predetermined value, typically 20~40% of the full load current at the maximum input voltage. The formula of inductance value is as below:
I L = 0.2 ~ 0.4 x I OUT ( MAX )
L=
VOUT VOUT 1 - f x I L VIN

I PK = I O +
(V - VOUT ) x t ON I L = I O + IN 2 2x L
Power Good Indicator with Adjustable Time Delay The PG and /PG pin terminal is an open drain output of N-MOS. Connect a resistor from PG and /PG pin to VCC or OUT1 to create a logic signal. If OUT1 pin is less than 2.97V (typ.) this pin is pulled to ground. When OUT1 pin is above 2.97V and with a delay time this pin is open. PG and /PG pin is forced low when in UVLO. The formula of adjustable delay time is as below : 0.8 delay - time = C x I DELAY
The Dissipation The power loss is given by:
2 2 PLOSS ( DC - DC ) = I OUT 1 x RDS (ON )- P x D + I OUT 1 x RDS (ON ) - N x (1 - D) + VIN x I OUT 1 x (t r + t f ) x f s + I s x VIN
PLOSS ( LDO ) = I OUT 2 x (VOUT 1 - VOUT 2 )
TJ ( MAX ) = T A + JA x ( PLOSS ( DC - DC ) + PLOSS ( LDO ) )
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO
Inductance(H) 3.3 4.7 3.3 3.3 4.7
Inductors Surface Mount Manufacturer/Part No. Sumida CDRH4D28-3R3 Sumida CDRH5D18-4R7 Mitsumi C3-K1.8L-3R3 Mitsumi C4-K1.8L-3R3 ABC SH40283R3YSB ABC SH40284R7YSB Capacitors Surface Mount Manufacturer/Part No. TDK C3216X5R0J226M TDK C3225X5R0J46M GRM42-6X5R 106K6.3 TAIYO LMK212BJ225MD TAIYO JMK212BJ475MG
Manufacturer Website www.sumida.com www.mitsumi.co.jp www.atec-group.com
Capacitance(F) 22 47 10 2.2 4.7
Manufacturer Website www.tdk.com www.tdk.com www.murata.com www.t-yuden.com www.t-yuden.com
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO PC Board Layout
1. The most critical aspect of the layout is the placement of the input capacitor C2. It must be placed as close as possible to the AT1367A/B/C/D to reduce the input ripple voltage. 2. Power loops on the input and output of the converter should be laid out with the shortest and widest traces possible. The longer and narrower the trace, the higher resistance and inductance it will have. The length of traces in series with the capacitors increases its ESR and ESL and reduces their effectiveness at high frequency. 3. The OUT1 pin should connect to C1 directly. And the route should be away from the noise source, such as inductor of SW line. 4. Grounding all components at the same point may effectively reduce the occurrence of loop.
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Package Outline : DFN10
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AT1367A/B/C/D
Preliminary Product Information 1MHz, 800mA Synchronous Buck Converter With Power Good Detector & LDO Reflow Condition (IR/Convection or VPR Reflow)
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat -Temperature Min(Tsmin) -Temperature Max (Tsmax) -Time (min to max)(ts) Time maintained above: -Temperature (TL) -Time (tL) Peak/Classification Temperature(TP) Time within 5C of actual Temperature (tP) Ramp-down Rate Time 25C to Peak Temperature Peak Sn-Pb Eutectic Assembly 3C/second max. Pb-Free Assembly 3C/second max.
100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max.
150C 200C 60-180 seconds 217C 60-150 seconds See table 2 10 seconds max. 6C/second max. 8 minutes max.
*All temperatures refer to topside of the package, measured on the package body surface.
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process -Package Peak Reflow Temperatures Package Thickness <2.5mm 2.5mm Volume mm <350 240+0/-5 225+0/-5
3 3
Volume mm3350 225+0/-5 225+0/-5 Volume mm3>2000 260+0 245+0 245+0
Table 2. Pb-free Process -Package Classification Reflow Temperatures Package Thickness <1.6mm 1.6mm - 2.5mm 2.5mm Volume mm <350 260+0 260+0 250+0 Volume mm3 350-2000 260+0 250+0 245+0
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0. For example 260+0) at the rated MSL level.
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